The invention relates to a semiconductor memory, and more particularly, to a multi-bit data DRAM cell array.
Referring to FIG. 1, a conventional dynamic random access memory (DRAM) 100 employs a hierarchical data bus (GDB, MDB) structure. The DRAM 100 comprises a plurality of column decoders 1, a plurality of cell arrays 2, and a plurality of column select lines CL extending from the column decoders 1 over the cell arrays 2. Each column decoder 1 is connected to a corresponding cell column select line CL. Each cell array 2 includes a plurality of memory cells, not shown. The cell arrays 2 are connected to sense-amp rows 3 each of which includes a plurality of sense-amps 4. The sense-amp rows 3 are connected to data buffers 5 via data buses GDB which extend parallel to the column select lines CL. The data buffers 5 are in turn connected to a main data bus MDB which extends in a direction orthogonal to the data buses GDB.
When a memory cell is selected by the column select line CL, a corresponding sense-amp 4 in the sense-amp row 3 amplifies data from the selected memory cell and provides it to the data bus GDB. Data on the data bus GDB is fed to the main data bus MDB via the data buffer 5.
A sense-amp pitch P or its layout pitch is defined in terms of the breadth occupied by a pair of adjacent sense-amps 4. In this instance, the layout pitch P is substantially equal to a spacing between two adjacent column select lines CL. On the other hand, the column decoder 1 has a breadth equal to the layout pitch P. When the column decoders 1 comprise a simple circuit with a reduced number of elements, it is possible to locate or place the column decoders 1 well within the constraint of the layout pitch P.
When it is desired to deliver multi-bit data to a peripheral circuit rapidly, the column decoders 1 are replaced by data buffers 5, as shown for the DRAM 110 in FIG. 2. Also, the column select lines CL are replaced by data buses GDB extending over the cell arrays-2. The number of sense-amps 4 connected to each data bus GDB is generally either two or four for each row 3 (two being shown in FIG. 2). The layout pitch P is defined by a spacing between two adjacent data buses GDB which is substantially equal to the breadth occupied by a pair of adjacent sense-amps 4. In this instance, it is necessary that the breadth for each data buffer 5 be defined by the layout pitch P.
However, it is noted that the data buffer 5 represents a differential amplifier circuit designed to detect and amplify a minimal potential. Because of the increased complexity of the circuit design for the data buffer 5 in comparison to the column decoder 1 shown in FIG. 1, it is difficult to establish the breadth of the data buffer 5 according to the layout pitch P. If an attempt is made to force the breadth of the data buffer 5 into conformity with the defined layout pitch P, a symmetry in the circuit of the data buffer 5 is lost, leading to inaccuracy of data detection. One solution would be to increase the number of sense-amps 4 connected to a single data buffer 5, thus effectively increasing the layout pitch P. However, an increased number of sense-amps 4 connected to each data buffer 5 results in an increase in the load on the data buffer 5, which is undesirable.
It is an object of the invention to provide a semiconductor memory and a method of controlling data therefrom which facilitate the layout of data buffers.